Ethernet device and method for extending ethernet FIFO buffer

ABSTRACT

A method and ethernet device is disclosed and includes an extended FIFO buffer. The link partner within the ethernet system is in communication with data terminal equipment (DTE). The speed of the link partner determined using a first packet received within the FIFO buffer. Subsequent FIFO buffer reading is optimized based on the determined speed of the link partner, thus for enhancing the inter-packet gap space usage.

FIELD OF THE INVENTION

[0001] This invention relates to the field of ethernet systems, and moreparticularly, this invention relates to extended FIFO buffers used inethernet systems and devices.

BACKGROUND OF THE INVENTION

[0002] Ethernet local area network (LAN) systems are becomingincreasingly popular because the open standards associated with ethernetsystems make this network available to almost everyone having a desirefor networked computer systems. An ethernet interface can normallyoperate at 10 megabits per second (Mbps), and at fast ethernet speedsthe interface operates at 100 Mbps, making it suitable for a widevariety of applications. Different computers can be linked withvendor-neutral network technology. The ethernet standard is formalizedas IEEE 802.3 Carrier Sense Multiple Access with Collision Detection(CSMA/CD) access method of the physical layer specifications developedby the Institute of Electrical and Electronic Engineers, and adopted bythe International Organization for Standardization (ISO). The ethernetsystem includes a physical medium to carry the ethernet packet signalsbetween computers, a set of medium access control rules embedded in eachethernet interface, and an ethernet frame or packet that is astandardized set of bits to carry data over the system.

[0003] An ethernet system includes a number of Data Terminal Equipment(DTE), typically computers, which are connected in the network. EachData Terminal Equipment includes a port having a physical layer and aMedia Access Control (MAC) typically connected by an n-pin connector(e.g., a 40-pin connector), via a media independent interface (MII), toa physical layer device (PHY), such as a transceiver, as known to thoseskilled in the art. This ethernet device includes a First-In, First-Out(FIFO) buffer that is also operable with a Medium Dependent Interface(MDI), such as a twisted-pair connector or fiberoptic connector. Atypical connector includes an RJ-45 connector connected to the physicalmedium that carries the ethernet signals. Other optical connectors canalso be used, depending on the design.

[0004] As known to those skilled in the art, an inter-packet gap (IPG)space is required as the FIFO buffer receives and empties data frompackets. A physically-large FIFO buffer cannot be used in ethernetapplications because a larger FIFO buffer violates the smallest possibleinter-packet gap (IPG) space as the buffer receives the packets. TheFIFO buffers are necessary when used with a media independent interface(MII), including a serial mode independent interface (SMII) and reducedmedia independent interface (RMII). The standard system clock is drivenfrom the media access control (MAC), which implements two clock domains.Thus, data is buffered through the FIFO buffer. Because the timeseparation between clock domains is small, the FIFO buffers used in theethernet systems are not large and can be about 64 bits.

[0005] In prior art devices, the FIFO buffer was always receiving datauntil it was half-full and configured to work with a half-full pointer.Thus, a good portion of the FIFO buffer remained unused and theinter-packet gap (IGP) space size was not efficiently configured.

SUMMARY OF THE INVENTION

[0006] The present invention advantageously extends the ethernet FIFObuffer such that it can be operated in an extended mode where it appearsto be larger while avoiding the limitations that are associated withlarger FIFO designs used in typical ethernet applications. A large FIFObuffer has greater tolerance for handling link partner and local devicefrequency variances without violating the smallest possible inter-packetgap space. Thus, the present invention provides an advantageousimprovement over standard, prior art ethernet FIFO buffers that waiteduntil the FIFO buffer was half full until it began to empty out. In thepast previous prior art systems, this was required because it wasunknown whether the link partner was faster or slower. In the extendedmode operation of the present invention, the FIFO buffer uses the firstpacket transfer to determine the speed of a link partner and dynamicallyreconfigures itself to optimize read controls based on the speed of thelink partner. For example, if the link partner is operating faster, thensubsequent FIFO buffer reading could begin, as an example, after onlythe first nibble, i.e., 4 bits, have been written. Thus, the FIFO buffercan use much of its full size to buffer data and increase the ability ofphysically smaller FIFO buffers to obtain greater tolerance ratings andenhance the inter-packet gap space usage.

[0007] In accordance with the present invention, the method extends theethernet FIFO buffer in a physical layer device of an ethernet systemhaving data terminal equipment (DTE) and a media access control (MAC)and connected by a media independent interface (MII) to the physicallayer device. The speed of a link partner in communication with dataterminal equipment (DTE) is determined, using a first packet receivedwithin the FIFO buffer. Subsequent reading of the FIFO buffer isoptimized based on the determined speed of the link partner, thusenhancing the inter-packet gap space usage.

[0008] In one aspect of the present invention, the step of optimizingany subsequent reading of the FIFO buffer comprises the step ofreconfiguring a half-full pointer used with the FIFO buffer. Any readingof the FIFO buffer can occur at the next succeeding packet receivedafter the first packet. The FIFO buffer can be read after only a firstnibble of 4 bits has been written therein when the link partner has beendetermined to be running faster.

[0009] In yet another aspect of the present invention, the mediaindependent interface (MII) comprises one of a serial media independentinterface (SMII) or reduced media independent interface (RMII). Togglebits associated with the packets and media independent interface datacan be used as control bits to identify whether the slots within theFIFO buffer are valid. For example, a control bit can be used toidentify an incoming packet as a valid packet. In this type of ethernetapplication, the media access control (MAC) is operated with a referenceclock, and media independent interface (MII) is operated with arecovered clock. An n-pin connector, such as a 40-pin or otherconnector, could connect the media independent interface (MII) to themedia access control (MAC) as is known to those skilled in the art.

[0010] In yet another aspect of the present invention, the FIFO bufferis filled to a half-full position with the first packet received withinthe FIFO buffer. This can occur by evaluating toggle bits of a firstpacket received within the FIFO buffer. The number of slots that remainto be read before the FIFO buffer is empty can be determined. Thisallows the speed of the link partner in communication therewith to bedetermined. Based upon the determined speed of this link partner, in oneaspect of the present invention, the half-full point is reconfigured foroptimizing subsequent reading of the FIFO buffer.

[0011] In yet another aspect of the present invention, an ethernetdevice includes a physical layer device having a FIFO buffer and mediaindependent interface (MII) connection to a media access control (MAC).A FIFO read/write mechanism reads and writes data to the FIFO buffer,such that the FIFO buffer is read based upon the determined speed of thelink partner in communication therewith, thus enhancing inter-packet gapspace usage. In one aspect, the FIFO buffer is read at the beginning ofa received packet when the link partner speed is determined to befaster. The FIFO buffer also includes a half-full pointer that isreconfigured based on the determined speed of a link partner forenhanced inter-packet gap space usage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other objects, features and advantages of the present inventionwill become apparent from the detailed description of the inventionwhich follows, when considered in light of the accompanying drawings inwhich:

[0013]FIG. 1 is a block diagram of a portion of an ethernet systemshowing the port of a data terminal equipment (DTE) and an ethernetinterface having a physical layer device (PHY) such as a transceiver,and also showing a media independent interface (MII) and associatedcomponents.

[0014]FIG. 2 is a high level flow chart showing an example of the methodof the present invention.

[0015]FIG. 3 is a fragmentary, “start read” diagram for an extendedserial media independent interface (SMII) FIFO, as a non-limitingexample.

[0016]FIG. 4 is a timing diagram illustrating how one example of anextended FIFO buffer control mechanism works.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The present invention will now be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. Like numbers refer to like elements throughout.

[0018] The present invention advantageously extends the ethernet FIFObuffer such as used in a physical layer device (PHY) of an ethernetsystem having data terminal equipment (DTE) and a media access control(MAC) and connected by a media independent interface (MII) to thephysical layer device. The present invention enhances the inter-packetgap space usage. The speed of the link partner in communication with thedata terminal equipment (DTE) is determined using a first packetreceived within the FIFO buffer. Based upon this speed determination, anoptimized reading of the FIFO buffer is implemented, allowing enhancedinter-packet gap space usage.

[0019]FIG. 1 illustrates at 10 a high level block diagram of an ethernetsystem, showing physical device hardware in block format as dataterminal equipment (DTE) 12 (shown in dashed lines), such as a personalcomputer, which is connected to the ethernet system via an ethernetinterface 14. The data terminal equipment 12 includes a port 16 (shownin dashed lines) having a physical layer 18 and media access control(MAC) 20, as known to those skilled in the art. A buffer 22 can beconnected to the MAC as part of the terminal equipment as known to thoseskilled in the art.

[0020] A media independent interface 24 forms a type of data bus betweenassociated ethernet components. It could be connected to the dataterminal equipment (DTE) 12 by different connector devices, including ann-pin connector 26 (shown by dotted lines), e.g., a 40-pin connector, asused by many skilled in the art. The media independent interface (MII)is connected to the ethernet interface, which includes a physical layerdevice (PHY) 28 such as normally part of a transceiver as known to thoseskilled in the art, and having a transmit and receive First-In,First-Out (FIFO) buffer 30, including a Transmit FIFO 30 a and ReceiveFIFO 30 b. A read/write control circuit 36 provides control over thereading and writing of data into and out from the FIFO buffer 30. Thisphysical layer device 28 is operable with a medium dependent interface(MDI) 32, which could be formed as a twisted-pair connector, fiberopticconnector, or other connector, as known to those skilled in the art. Oneconnector example used by many skilled in the art is an RJ-45 connectorused as a medium dependent interface. The physical medium 34 carries theethernet data and is operable with the medium dependent interface 32.The medium independent interface (MMI), on the other hand, could be aserial media independent interface (SMII) or a reduced media independentinterface (RMII).

[0021] The medium independent interface (MII) 24 includes theelectronics that provide a means to link the ethernet media accesscontrol functions in a network device with the physical layer device(PHY), to transmit ethernet packet signals onto the network physicalmedium. The medium independent interface 24 can optionally support both10-Mbps and 100-Mbps operation. Signaling differences are transparentbecause of the design of the medium independent interface 24. Linesignals are translated into digital signals that are transmitted toethernet chips used in various ethernet network devices.

[0022] As known to those skilled in the art, the serial mediaindependent interface (SMII) and reduced independent interface (RMII)are both reduced interfaces from the standard media independentinterface. There are many FIFO buffer devices that support mediaindependent interfaces. At this time, a fewer number of devices supportthe reduced media independent interfaces, while the serial mediaindependent interface is relatively new. The reduced media independentinterface and serial media independent interface are advantageousbecause they achieve a reduced number of connector pins by increasingthe clock frequency.

[0023] It is known that these interfaces are operable on a standardsystem clock driven from the media access control (MAC) 20. For example,in the reduced media independent interface (RMII), the clock speed canbe doubled. In a serial media independent interface (SMII), the clockspeed can be quadrupled, and this allows time slicing of the mediaindependent interface data that enter an ethernet network device. In oneexample, the reduced media independent interface has half the systemspeed, while in another example, a serial media independent interfacehas one fifth the clock speed. Data is time sliced out from, forexample, four pins onto two pins, or even one pin in some examples,reducing the number of pins.

[0024] As the interface is implemented and reduced, two clock domainsare introduced, as known to those skilled in the art. The mediaindependent interface (MII) can operate on a recovered 20 megahertzclock, as a non-limiting example. It is recovered from the data streamfrom the link partner in communication therewith. A network device canbridge data over to a reduced media interface protocol that is on astandard reference clock from the media access control (MAC), whilerunning at a faster frequency. Thus, there are two clocks that are notsynchronized. Although the media independent interface is supposed to beat about 25 megahertz in one example, it is probably slightly slower orslightly faster, and as a result, it is not possible to perform astraight latching up and transmission over to the device. Thus, the datahas to be buffered through a FIFO buffer.

[0025] It has been conventional in a FIFO buffer in this type of systemto allow the FIFO buffer to become half-full. It is at this point intime that the device begins reading from the FIFO buffer through meansof an appropriate FIFO read/write control circuit. In this example, theentire portion of the packet is not buffered to the FIFO buffer. Thereis a minimal amount of clock timing difference between the two clockdomains. It is evident, then, that the FIFO buffer only has to be largeenough to buffer the amount of variation between the clocks. As aresult, because the variation is small, the FIFO buffers can typicallybe about 64 bits, as a non-limiting example.

[0026] As noted before, prior art FIFO buffers are normally allowed tobecome half-full before the network ethernet devices begin reading theFIFO buffer. In the prior art devices, a FIFO read/write control circuitdoes not know if the link partner in communication therewith is runningeither a little faster or a little slower. By allowing the FIFO bufferto become half full, it is possible to fill it up more, or it can becomeless full by the time the end of packet (EOP) is reached. Thus, the fullsize of the FIFO buffer is not used and only half the FIFO buffer isrealistically used.

[0027] The present invention extends the FIFO buffer 30 operating in anextended mode. The FIFO buffer 30 appears larger, while avoiding thelimitations of any larger FIFO buffer designs. The larger FIFO buffer 30has a greater tolerance for handling the link partner and local devicefrequency variances. A physically large FIFO buffer, however, cannot beused in ethernet applications because it will violate the smallestpossible inter-packet gap (IPG) space as it buffers the receivedpackets. In the present invention, a software register can be set to0×10 bit, as a non-limiting example, to enable this mode of operation tobe valid for both serial media independent interface or reduced mediaindependent interface modes of operation.

[0028] At the outset, the FIFO buffer 30 uses the first packet transferto determine a link partner speed. It then dynamically reconfiguresitself to optimize the control over reading the FIFO buffer 36 as basedupon the link partner speed. For example, if the link partner isdetermined to be running faster, then FIFO buffer reading would beginafter the first data nibble, i.e., the 4 bits has been written, as anon-limiting example. Thus, the FIFO buffer uses nearly the full buffersize to buffer the data and dramatically increase the ability of aphysically smaller FIFO buffer to obtain greater tolerance ratings.

[0029] As shown in the simplified flow chart of FIG. 2, a method of thepresent invention is operable and receives a first packet within theFIFO buffer 22 (block 100), and based on that first packet determinesthe speed of the link partner in communication therewith (Block 102). Itis only after determining the speed of the link partner using this firstpacket, that the FIFO buffer is reconfigured (Block 104). It is evidentthat the FIFO buffer 22 starts off in the initial mode where the bufferis half filled with the first packet. The FIFO buffer then dynamicallyreconfigures itself. For example, if the link partner is determined tobe faster, then the FIFO read/write control circuit 36 can begin readingthe FIFO buffer when the second or subsequent packet initially arrives,such as after the first nibble of 4 bits has been written therein.

[0030] This optimization of the subsequent read operation of the FIFObuffer can occur, for example, by reconfiguring a half-full pointer usedwith the FIFO buffer, by techniques known to those skilled in the art.It is well known that the size of the FIFO buffer determines how largean inter-packet gap space can be handled at the ethernet interface. Thisis valid because at the end-of-packet (EOP), no matter how full the FIFObuffer is, there are many cycles that are required to empty out the FIFObuffer and prepare it for the next packet. Thus, the FIFO buffer isemptying out data into this inter-packet gap space within the ethernetenvironment between the frames (i.e., between the packets.) Thus, ifthere is a smaller FIFO buffer, it will empty out fewer bytes and as aresult, it can empty out in a smaller inter-packet gap space to handle amore congested environment. Thus, more information can be placed on theethernet environment even when there is greater traffic.

[0031]FIG. 3 illustrates an extended serial medial independent interfaceFIFO “start read” diagram where the link partner has been found to befaster. This fragmentary diagram gives an example of two clock domains,such as the SCLK domain, i.e., the Synchronous with Clock Domain, whichcorresponds to the system clock (or reference clock) with the mediaaccess control 20. The RXC domain is the recovered clock domain that isassociated with the media independent interface (MII) clock. The diagramillustrates how the FIFO buffer 30 can reconfigure itself after it hasdetected that the link partner is either slow or fast. The read andwrite toggle (wr_tggl_in; rd_tggl_in) is specific to one type of design,as a non-limiting example, and illustrates how toggle bits are used ascontrol bits to identify each slot as being valid or not. The continuousstream of small frames or slots can be available for use by variousdevices and nodes in which access to a transmission medium may beorganized. Typically, slots are known as a few tens or hundreds of bitslong and can be marked full or empty. The device can receive an emptyslot and fill it with data, set source and destination addresses, andmark it full. The elasticity buffer is also illustrated as part of theread and write with a write and read pointer. A horizontal linebeginning with WO and ending with R2 illustrates the address components,including Write (W), Buffer (B) and Read (R), as known to those skilledin the art.

[0032]FIG. 4 illustrates a timing diagram showing on the top horizontalline the Synchronous with Clock Domain (SCLK) followed vertically downby the various timing lines extending horizontally across, including thesecond line for the rx-dv (valid), which is basically the control bitthat identifies an incoming packet as being a valid packet.

[0033] Lines 3 and 4 illustrate the write and read toggle buffer(wr_tggl_buff; rd_tggle_buff). Line 5 is the fast rxd that is thecontrol signal indicating that the link partner has been detected asfaster in this particular example. A half full pointer (half_full_ptr[3:0]) is then illustrated.

[0034] It is evident that the present invention now allows the FIFObuffer in a physical layer device of an ethernet system having dataterminal equipment (DTE) and a media access control (MAC) to be expandedwhen operable with a media independent interface (MII) to the physicallayer device. In one aspect, the speed of the link partner is determinedand subsequent reading of the FIFO buffer is optimized based on thedetermined speed of the link partner for enhancing the inter-packet gapspace which can occur by reconfiguring a half-full pointer used the FIFObuffer.

[0035] Many modifications and other embodiments of the invention willcome to the mind of one skilled in the art having the benefit of theteachings presented in the foregoing descriptions and the associateddrawings. Therefore, it is to be understood that the invention is not tobe limited to the specific embodiments disclosed, and that themodifications and embodiments are intended to be included within thescope of the dependent claims.

That which is claimed is:
 1. A method of extending the FIFO buffer in aphysical layer device of an Ethernet system having data terminalequipment (DTE) and a media access control (MAC) and connected by amedia independent interface (MII) to the physical layer devicecomprising the steps of: determining the speed of a link partner withinthe Ethernet system in communication with data terminal equipment (DTE)using a first packet received within the FIFO buffer; and optimizingsubsequent reading of the FIFO buffer based on the determined speed ofthe link partner for enhancing the inter-packet gap space usage.
 2. Amethod according to claim 1 wherein the step of optimizing subsequentreading of the FIFO buffer comprises the step of reconfiguring ahalf-full pointer used with the FIFO buffer.
 3. A method according toclaim 1 and further comprising the step of optimizing any reading of theFIFO buffer at the next succeeding packet received after the firstpacket.
 4. A method according to claim 1 and further comprising the stepof reading the FIFO buffer after only a first nibble of four bits hasbeen written therein when the link partner has been determined to berunning faster.
 5. A method according to claim 1 wherein the mediaindependent interface (MII) comprises one of a serial media independentinterface (SMII) or reduced media independent interface (RMII).
 6. Amethod according to claim 1 and further comprising the step of usingtoggle bits as control bits to identify whether slots within the FIFObuffer are valid.
 7. A method according to claim 1 and furthercomprising the step of using a control bit to identify an incomingpacket as a valid packet.
 8. A method according to claim 1 and furthercomprising the step of operating the media access control (MAC) with areference clock and operating the media independent interface (MII) witha recovered clock.
 9. A method according to claim 1 and furthercomprising the step of connecting the media independent interface (MII)to the media access control (MAC) with an n-pin connector.
 10. A methodof extending the FIFO buffer in a physical layer device of an Ethernetsystem having data terminal equipment (DTE) and a media access control(MAC) and connected by a media independent interface (MII) to thephysical layer device comprising the steps of: determining the speed ofa link partner within the Ethernet system in communication with dataterminal equipment (DTE) after filling the FIFO buffer to a half-fullposition with a first packet received within the FIFO buffer; andoptimizing subsequent reading of the FIFO buffer based on the determinedspeed of the link partner for enhancing the inter-packet gap spaceusage.
 11. A method according to claim 10 wherein the step of optimizingsubsequent reading of the FIFO buffer comprises the step ofreconfiguring a half-full pointer used with the FIFO buffer.
 12. Amethod according to claim 10 and further comprising the step ofoptimizing any reading of the FIFO buffer at the next succeeding packetreceived after the first packet.
 13. A method according to claim 10 andfurther comprising the step of reading the FIFO buffer after only afirst nibble of four bits has been written therein when the link partnerhas been determined to be running faster.
 14. A method according toclaim 10 wherein the media independent interface (MII) comprises one ofa serial media independent interface (SMII) or reduced media independentinterface (RMII).
 15. A method according to claim 10 and furthercomprising the step of using toggle bits as control bits to identifywhether slots within the FIFO buffer are valid.
 16. A method accordingto claim 10 and further comprising the step of using a control bit toidentify an incoming packet as a valid packet.
 17. A method according toclaim 10 and further comprising the step of operating the media accesscontrol (MAC) with a reference clock and operating the media independentinterface (MII) with a recovered clock.
 18. A method according to claim10 and further comprising the step of connecting the media independentinterface (MII) to the media access control (MAC) with an n-pinconnector.
 19. A method of extending the FIFO buffer in a physical layerdevice of an Ethernet system having data terminal equipment (DTE) and amedia access control (MAC) and connected by a media independentinterface (MII) to the physical layer device comprising the steps of:evaluating toggle bits of a first packet received within the FIFObuffer; determining the number of slots that remain to be read beforethe FIFO buffer is empty; determining the speed of a link partner incommunication therewith; and reconfiguring a half-full pointer used withthe FIFO buffer for optimizing subsequent reading of the FIFO bufferbased on the determined speed of the link partner and enhancing theinter-packet gap space usage.
 20. A method according to claim 19 andfurther comprising the step of optimizing subsequent reading of the FIFObuffer at the next succeeding packet received after the first packet.21. A method according to claim 19 and further comprising the step ofreading the FIFO buffer after only a first nibble of four bits has beenwritten therein when the link partner has been determined to be runningfaster.
 22. A method according to claim 19 wherein the media independentinterface (MII) comprises one of a serial media independent interface(SMII) or reduced media independent interface (MII).
 23. A methodaccording to claim 19 and further comprising the step of using togglebits as control bits to identify whether slots within the FIFO bufferare valid.
 24. A method according to claim 19 and further comprising thestep of using a control bit to identify an incoming packet as a validpacket.
 25. A method according to claim 19 and further comprising thestep of operating the media access control (MAC) with a reference clockand operating the media independent interface (MII) with a recoveredclock.
 26. A method according to claim 19 and further comprising thestep of connecting the media independent interface (MII) to the mediaaccess control (MAC) with an n-pin connector.
 27. An ethernet devicecomprising: a physical layer device having a FIFO buffer and mediaindependent interface (MII) connection to a media access control (MAC);and a FIFO read/write control circuit for reading and writing data tothe FIFO buffer such that the FIFO buffer is read based on thedetermined speed of a link partner in communication therewith forenhancing inter-packet gap space usage.
 28. An ethernet device accordingto claim 27 wherein the FIFO buffer is read at the beginning of areceived packet when the link partner speed is determined to be faster.29. An ethernet device according to claim 27 wherein said FIFO bufferfurther comprises a half-full pointer that is reconfigured based on thedetermined speed of a link partner for enhanced inter-packet gap spaceusage.
 30. An ethernet device according to claim 27 wherein said mediaindependent interface (MII) comprises one of a serial media independentinterface (SMII) or reduced media independent interface (RMII).
 31. Anethernet device according to claim 27 and further comprising a recoveredclock for the media independent interface (MII) based on a system clockassociated with the media access control (MAC).